High Performance Floating-point DSPC
ER-DSPC-20A processor is the second generation independent high performance floating-point digital signal processor. On the basis of "ER-DSPC-10", the processor core, command system and peripheral interface are fully upgraded, and the computing power reaches 100 billion floating point operations per second, which is 6 times over the performance of first generation"ER-DSPC-10". It is the DSP with the highest single-core computing performance on the market, and be able to widely used on radar,electronic countermeasures, communications, image processing and other fields.
Technical Characteristics
Dual-core architecture, rich interface;
Directly connected to AD/DA to form a minimum system;
Autonomous embedded operating system.
Typical Technical Indicators
DSP Frequency: 500MHz
Computing Performance: 84GFLOPS
On-chip Storage: 105Mbit
Communication Bandwidth: 224Gbps
Typical Power Consumption: 10W
| Compared With Similar Products FFT Performance | |||
| Input Points | C66x Operation Cycle | Single Core Operation Cycle | Cycle Number Ratio |
| 1k | 6472 | 980 | 6.6 |
| 2k | 17500 | 2510 | 6.9 |
| 4k | 43125 | 6275 | 6.8 |
| 64k | 696588 | 103968 | 6.7 |
Interface List
| IO Type | Performance Parameter | |
| DDR | Particle Type | DDR3/4 |
| External Data Width | 64bit | |
| Number of Controllers | 2 | |
| Maximum Total Bandwidth | 128 Gbps@500MHz | |
| PCIE | Support Protocol Version | GEN1/2/3 |
| Number of LANE | 4 | |
| Maximum Bandwidth | 64 Gbps | |
| RapidIO | Support Protocol Version | 2.1 |
| Number of LANE | 4 | |
| Number of Controllers | 2 | |
| Maximum Total Bandwidth | 80 Gbps | |
| HX-Link (Custom protocol) | Support Protocol Version | 1.0 |
| Number of LANE | 4 | |
| Number of Controllers | 2 | |
| Maximum Total Bandwidth | 80 Gbps | |
| JESD204B (The controller which reuse HX-Link) | Support Protocol Version | JESD 204B |
| Number of LANE | 4 | |
| Number of Controllers | 1(AD/DA) | |
| Maximum Total Bandwidth | 32 Gbps | |
| Ethernet | / | 10/100/1000MHz Ethernet, RGMII |
| Parallel Port (EMIF) | / | 4bit chip select, 26bit address, 32bit data |
| GPIO | / | 64bit |
| UART/I2C/SPI | Support | |
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