Strong Driving Force CPU

Strong Driving Force CPU

ER-CPU-35A/35B
1. Based on New Arch™;
2. High bandwidth memory interface: Support DDR4-3200, the actual bandwidth is more than 25GB/s;
3. Integrated Eco-compatibility: Real-time translation for applications with different architectures.

Strong Driving Force CPU

Strong Driving Force CPU

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    Strong Driving Force CPU

    Introduction

    ER-CPU-35A/35B is a general processor for personal computers, servers and other information fields. The product uses unique Arch™ processor core to further increase frequency, reduce power consumption, and optimize performance. While maintaining pin compatibility with the ER-CPU-34A processor, the frequency is increased to 2.5GHz, power consumption is reduced by more than 30%, and performance is improved more than 50%. The ER-CPU-35B supports multiple interconnect based on the ER-CPU-35A.

    Main Features

    Based on New Arch™

    The single-core SPEC CPU 2006 Base has a measured performance of more than 26 points, making it the most efficient domestic processor core

    High bandwidth memory interface: Support DDR4-3200, the actual bandwidth is more than 25GB/s

    Integrated Eco-compatibility: Real-time translation for applications with different architectures

    Refined power consumption management: Built-in power consumption control core which can adjust dynamically frequency and voltage

    Support for independent GPU: Equipped with the new generation of independent display bridge 7A2000, using self-designed 3D GPU

    Parameters

    Master frequency2.3GHz-2.5GHz
    Peak operation speed160GFlops
    Core number4
    Processor core

    64-bit superscalar processor core EA464;

    Support for Arch™ instruction system;

    Support 128/256-bit vector instruction;

    Four launch out of order execution;

    4 fixed point units, 2 vector units and 2 access storage units

    High-speed Cache

    Each processor core contains a 64KB private level-1 instruction cache and 64KB private level-1 data cache;

    Each processor core contains 256KB private level-2 cache;

    All processor cores share 16MB level-3 cache

    Memory controller

    Two 72-bit DDR4-3200 controllers;

    Support ECC verification

    High speed I/O

    2 HyperTransport 3.0 controllers;

    Support multi-processor data consistency interconnection (CC-NUMA)

    Other I/ O1 SPI, 1 UART, 2 I2C, 16 GPIO interfaces
    Power consumption management

    Support the main module clock dynamic shutdown;

    Support the main clock domain dynamic frequency conversion;

    Supports dynamic voltage regulation in the main voltage domain.

    Typical power consumption35W@2.5GHz

     

    Application Techniques

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