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Application

How to Configure the Register of Ericco MEMS Gyro

High Performance MEMS Gyroscope

1.Application products

North seeking MEMS Gyro ER-MG2-100

Navigation grade MEMS Gyro ER-MG2-300/400

2.Register format introduction:

MEMS gyro register address (absolute address) access consists of page and address offset. Page is a single byte, and the available values range from 0 to 1. The address offset is 6 bits and the range is 0x00~0x3E. 0x3F sets the register address as the "page". This address maps to page 0 only and is not affected by the Page setting.

The register page needs to be modified when the absolute register address exceeds 0x3F. The setting to write the corresponding page value to the register page is at address 0x3F.

Page 0000102030405060708090A0B0C0D0E0Foffset address
000102030405060708090A0B0C0D0E0FRegister address
101112131415161718191A1B1C1D1E1Foffset address
101112131415161718191A1B1C1D1E1FRegister address
202122232425262728292A2B2C2D2E2Foffset address
202122232425262728292A2B2C2D2E2FRegister address
303132333435363738393A3B3C3D3E3Foffset address
303132333435363738393A3B3C3D3E3FRegister address
Page 1000102030405060708090A0B0C0D0E0Foffset address
404142434445464748494A4B4C4D4E4FRegister address
101112131415161718191A1B1C1D1E1Foffset address
505152535455565758595A5B5C5D5E5FRegister address
202122232425262728292A2B2C2D2E2Foffset address
606162636465666768696A6B6C6D6E6FRegister address
303132333435363738393A3B3C3D3E3Foffset address
707172737475767778797A7B7C7D7E3FRegister address

Table 3 Register format

The default register page is Page 0, which accesses the contents of the register's absolute address range 0x00~0x3F.When a register with an absolute azimuth address greater than 0x3F is needed, the page register (0x3F) needs to be modified and then accessed according to the offset address.

For example, if you want to access the absolute register address 0x40, you need to write the address 0x3F to 0x01 through SPI, and then SPI operates on the address 0x00.

Note: Because some bits in registers are defined as reserved, they usually have default values on them and may affect the actual function and performance of the chip.When modifying part of the register, it is necessary to carry out read-change-write operation, that is, read the register first and write back the corresponding bit modified.

3.Register content description

Register absolute address: 0x2E, STATUS

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
reserveData_Rdyreservereservereservereservereservereserve
Sensor data status flag. Data_Rdy1. Effective sensor data;
0, the sensor data is invalid;

Register absolute address: 0x30, TEMP_OUT_L

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Temp_OUT [7:0]
Sensor temperature output, low 8 bit.

Register absolute address: 0x31, TEMP_OUT_H

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Temp_OUT [15:8]
Sensor temperature output, high 8 bits

Register absolute address: 0x32, Rate_OUT_L

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Rate_OUT [7:0]
Sensor angular velocity output, Bit 7:0

Register absolute address: 0x33, Rate_OUT_M

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Rate_OUT [15:8]
Sensor angular velocity output, Bit 15:8

Register absolute address: 0x34, Rate_OUT_H

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Rate_OUT [23:16]
Sensor angular velocity output, Bit 23:16

Register absolute address: 0x3F, Addr_Page_Sel

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Addr_Page_Sel [7:0]
Register address access page Settings:
0: Absolute address range of the accessible register: 0x000 ~ 0x03E
1: Absolute address range of the accessible register: 0x040 ~ 0x07E

Register absolute address: 0x49, Chip ID 1

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CHIP_ID_1: 0x41
Chip ID 1. Default: 0x41

Register absolute address: 0x4A, Chip ID 2

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CHIP_ID_2: 0x01
Chip ID 2. Default: 0x01

Register absolute address: 0x4C, OTP_ID_0

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_0
OTP identifies ID 0

Register absolute address: 0x4D, OTP_ID_1

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_1
OTP identifies ID 1

Register absolute address: 0x4E, OTP_ID_2

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_2
OTP identifiesID 2

Register absolute address: 0x4F, OTP_ID_3

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_3
OTP identifiesID 3

Register absolute address: 0x50, OTP_ID_4

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_4
OTP identifies ID 4

Register absolute address: 0x51, OTP_ID_5

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
OTP_ID_5
OTP identifies ID 5

The value of the OTP identification ID is determined by factory Settings.

Register absolute address: 0x59, SYNC_BW_SEL

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
reservereservereservereservereservereserveSync_ODR_SelBW _Sel
External synchronization and output bandwidth Settings selection.
Sync_ODR_Sel, external synchronization input parameter selection, 0: synchronization input and update rate parameter use synchronization setting register value;
1: OTP is used for synchronous input and update rate parameters;
BW_Sel, output bandwidth parameter selection, 0: Output bandwidth parameter USES bandwidth to set the register value;
1: The output bandwidth parameter USES OTP burning content;

Register absolute address: 0x6A, SYNC_CTRL

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
reserveODR_RATE[2:0]DRY_PolarSync_PolarSync_Mode [1:0]
data updating rate：

ODR_RATE：

0：2000 Hz

1：1000 Hz

2：500 Hz

3：250 Hz

4：125 Hz

5：62.5 Hz

6：6000 Hz

7：12000 Hz

Synchronous input control.
DRY_Polar: Data Ready outputs interrupt polarity.0: When the data is valid, the interrupt pin output is low;
1: When the data is valid, the interrupt pin output is high;
Sync_Polar: External synchronization of input signal polarity.0: The falling edge is effective;
1: The rising edge is valid;
Sync_Mode: Synchronous signal source selection.0: Adopt internal synchronization signal;
1. Adopt external synchronization signal;

Register absolute address: 0x6B, SYNC_DIV_L

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
SYNC_DIV [7:0]
Low frequency quotient of synchronous signal input.

Register absolute address: 0x6C, SYNC_DIV_H

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
SYNC_DIV [15:8]
Synchronous signal input frequency division factor is high byte.
Frequency division coefficient of external synchronization signal, input range: 0~65535;
After external synchronization signal is adopted, ODR frequency:That is, when the frequency division coefficient is 0, the ODR is half of the frequency of the external synchronous clock.

Register absolute address: 0x6D, BW_CTRL

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
reservereserveLPF SEL[1:0]BW_CRTL[3:0]
Low pass filter series selection:

LPF_ODR:

0: LPF 1 is enabled

1: LPF 1 and LPF 2 are enabled

2: Enable LPF 1, LPF 2, and LPF 3

3: Disables all low-pass filters

Output bandwidth control

BW_CTRL：

0：12.5 Hz

1:25Hz

2:50Hz

3:100Hz

4:150Hz

5:200Hz

6:250Hz

7:300Hz

 

 

8:350Hz

9:400Hz

10:450Hz

11:500Hz

12:550Hz

13:600Hz

14:700Hz

15:800Hz

More Technical Questions

1.How accurate is MEMS gyroscope?

2.Where are MEMS Gyroscopes Used?

3.What is a MEMS Gyroscope?

4.What is the Hardware Interface of Ericco MEMS Gyro

5.What Data Format is High Performance MEMS Gyro

6.How to Weld and Install High Performance MEMS Gyro

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